A static random access memory (SRAM) has the advantages of low power consumption and fast operating speed compared to a dynamic RAM (DRAM). Accordingly, the SRAM is widely employed in a portable appliance or a cache memory device of a computer. A unit cell of the SRAM is mainly classified into two types. One of them is a high load resistor SRAM cell, which employs a high load resistor as a load device, and the other is a CMOS SRAM cell, which employs a P-channel MOS (PMOS) transistor as a load device. The CMOS SRAM cell is again classified into two types. One of them is a thin film transistor (TFT) SRAM cell which employs a TFT formed on a semiconductor substrate as a load device, and the other is a bulk CMOS SRAM cell which employs a bulk transistor formed in a semiconductor substrate as a load device. The bulk CMOS SRAM cell has high cell stability compared to the TFT SRAM cell and the high load resistor SRAM cell. That is, the bulk CMOS SRAM cell has good low voltage characteristics and low standby current. This is possible because all transistors constituting the bulk CMOS SRAM cell are formed on a single crystalline silicon substrate whereas the TFT is generally fabricated using a polysilicon layer as a body layer, which may have higher leakage characteristics. However, the bulk CMOS SRAM cell has a relatively low integration density compared to the TFT SRAM cell.
Even though the TFT SRAM cell has a higher integration density than the bulk CMOS SRAM cell, the integration density of the TFT SRAM cell is still lower than the integration density of the DRAM cell. Accordingly, in order to implement a highly integrated SRAM device having high reliability, it is typically necessary to design a compact cell having a three-dimensional structure.
An SRAM cell having a three dimensional structure formed using multiple-gate transistors is disclosed in U.S. Patent Publication No. 2004/99885 to Yeo et al., entitled “CMOS SRAM cell configured using multiple-gate transistors.” According to Yeo et al., gate electrodes are formed at both sides of silicon bodies facing each other to configure multiple-gate field effect transistors (FETs). The multiple-gate FETs are pull-down transistors or pull-up transistors of the SRAM cell. FIG. 1 illustrates a conventional CMOS SRAM cell. Referring to FIG. 1, the CMOS SRAM cell includes a pair of driver transistors TD1 and TD2, a pair of transfer transistors TA1 and TA2, and a pair of load transistors TL1 and TL2. The driver transistors TD1 and TD2 and the transfer transistors TA1 and TA2 are NMOS (PMOS) transistors and the load transistors TL1 and TL2 are PMOS (NMOS) transistors. A source region of the first driver transistor TD1 is connected to a ground line Vss, and a drain region of the first transfer transistor TA1 is connected to a first bit line BL1. Similarly, a source region of the second driver transistor TD2 is connected to the ground line Vss, and a drain region of the second transfer transistor TA2 is connected to a second bit line BL2.
Source and drain regions of the first load transistor TL1 are connected to a power supply line Vcc and a drain region of the first driver transistor TD1, respectively. Similarly, source and drain regions of the second load transistor TL2 are electrically connected to the power supply line Vcc and a drain region of the second driver transistor TD2, respectively. The drain region of the first load transistor TL1, the drain region of the first driver transistor TD1, and the source region of the first transfer transistor TA1 are connected together at a first node N1. In addition, the drain region of the second load transistor TL2, the drain region of the second driver transistor TD2, and the source region of the second transfer transistor TA2 are connected together at a second node N2. The first and second nodes N1 and N2 act as storage nodes of the SRAM cell. A gate electrode of the first driver transistor TD1 and a gate electrode of the first load transistor TL1 are connected to the second node N2, and a gate electrode of the second driver transistor TD2 and a gate electrode of the second load transistor TL2 are connected to the first node N1. In addition, gate electrodes of the first and second transfer transistors TA1 and TA2 are connected to a word line WL.
The drain region of the first load transistor TL1 is electrically connected to the drain region of the first driver transistor TD1 via the first node N1. Similarly, the drain region of the second load transistor TL2 is electrically connected to the drain region of the second driver transistor TD2 via the second node N2. Accordingly, the first load transistor TL1 and the first driver transistor TD1 are connected in series to form a first inverter. Similarly, the second load transistor TL2 and the second driver transistor TD2 are connected in series to form a second inverter. Accordingly, the first and second inverters are cross-coupled to form one latch circuit.